Classiq challenge / Circuit design
An 18-qubit phase oracle exploiting the structure of a 64 × 64 logo, with exhaustive numerical verification.
The final circuit ↗Circuit depth
5,329111≈48× shallower
18 qubits · 557 CX gates
Exploit the image structure
The pipeline makes the load–phase–uncompute structure explicit. Cleaning the ancillary register is part of implementing the intended oracle.
distinct row and column patterns, each represented by a four-bit class code. Repetition in the image becomes structure in the circuit.
The optimization history shows depth and gate count changing together. The final depth of 111 is a completed construction, not a proof that shallower circuits are impossible.
The schedule shows how operations are arranged around dependency and ready-time constraints. This is why two circuits with similar gate counts can have different depths.
| Measurement | Baseline | Final |
|---|---|---|
| Circuit depth | 5,329 | 111 |
| CX gates | 3,502 | 557 |
| Verified inputs | — | 4,096 / 4,096 |
Exhaustively verified
Class-code loaders, a 63-term phase polynomial, and ready-time scheduling reduced the circuit to depth 111, with 557 CX and 423 U3 gates. All 4,096 valid inputs passed verification; six ancillas returned to zero. The largest numerical error was 5.57×10⁻¹⁴. Depth 111 is the best completed construction here, not a general lower bound.
Verification covers all valid inputs and checks both phase behavior and ancillary cleanup. The reported numerical error is measured up to a common global phase.
The oracle must assign the required phase to each of the 4,096 pixels of a 64 × 64 image while cleaning up its work qubits. Rather than treating every pixel independently, the construction uses the repeated row and column patterns: 11 classes can each be represented by a four-bit code. This reduces the structure that the central phase operation has to encode.
The circuit loads class codes, applies a 63-term phase polynomial, and reverses the loading computation. Gate count alone does not determine depth: the arrival time of each signal and the dependencies between operations also affect the schedule. Ready-time scheduling and loader/phase interfaces therefore form part of the optimization, followed by exhaustive verification of the completed circuit.
The challenge submission